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A comprehensive overview of microbursts and their impact on network performance, with a focus on Juniper's QFX5K EVO platforms (QFX5220, QFX5130, QFX5230, and QFX5240). Introduction In this article, we'll define microbursts and illustrate typical network topologies where they are likely to...
Packet Buffer Architecture on QFX5K-Series switches and various buffer tuning options available on these platforms to maximize the traffic burst absorption. Overview On QFX5K platforms all packets that enter the ingress pipeline will be stored at central MMU packet buffers before it...
A brief overview of the challenges faced in next-generation networking and data communication equipment using older Intermediate Bus Architecture (IBA) and a description of a forward-looking Power Delivery Architecture and its benefits related to overall sustainability goals that could set the...
A transit packet walkthrough inside an MX Series Trio 6 ASIC, with all the internal details on the different memory and components involved in the process. This article has been co-written by David Roy and Nicolas Fevrier. It's the first post of a Series on the Trio 6...
Express5 fungible shared memory architecture provides the foundation for a flexible memory scheme which increases scale and efficiency of memory utilization. Introduction Typically, a fixed pipeline architecture ASIC comes with fixed-size tables or memories for various applications in the...
PTX10002-36QDD is the first router equipped with the new Juniper Express5 packet forwarding engine, a new deep-buffer 28.8Tbps package introducing a lot of innovations and improvements compared to its predecessor. This post will answer a simple question: how fast can we program the FIB...
BIER Interoperability testing verified between PTX10002-36QDD and other vendors during the EANTC 2024. Introduction BIER – Bit Index Explicit Replication provides a multicast architecture with no per-tree multicast states in the core, by having the information...
High-level functionality description of BIER as MVPN provider tunnels in the upcoming release of PTX Express 5. Introduction In Cheers! Have a BIER , we explained how BIER [RFC8279] works and how it has come to a prime time for BIER deployment with the hardware capabilities from...
PTX Express 5 ASIC has full support for SRv6 with up to 8 carrier segment identifiers (SIDs) in a packet. That translates to 48 micro-SIDs (uSIDs), enough to pass a packet around the world! Following is a description of how SRv6 was implemented in the ASIC. Introduction The large-sized...
Express5 has leap frogged in terms of Route scale, thanks to a novel approach in implementing the route table memory. This article is part of a series of publications on Express5: Express 5 Overview: https://community.juniper.net/blogs/dmitry...