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Data plane and Trio Chipset on MX5

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  • 1.  Data plane and Trio Chipset on MX5

    Posted 10-27-2017 10:37

    Hi everyone,

    I am reading a great book " Juniper MX Series".   I have some questions:

     

    1)On MX5, when we speak of " Trio Chip Set Architecture" are we only talking about Data plane i.e whole data plane is based on this architecture or does it also include Control plane ?

    2) Does MX only supports Ethenet PIC or we can install SONET/ATM/Frame relay PIC as well?

     

    3) In the context of MX, When we use " INLINE SERVICE"  such as IP FLOW, NAT, GRE, BFD what exactly do we mean by " INLINE"? Are we saying these services are run from PFE not RE?

     

    Thanks and have a nice weekend!!

     

     



  • 2.  RE: Data plane and Trio Chipset on MX5
    Best Answer

    Posted 10-27-2017 11:03

    Hi,

     

    Please find the inline answers :

     

    1)On MX5, when we speak of " Trio Chip Set Architecture" are we only talking about Data plane i.e whole data plane is based on this architecture or does it also include Control plane ?

     

    It also includes control plane. 

     

    2) Does MX only supports Ethenet PIC or we can install SONET/ATM/Frame relay PIC as well? 

     

    MX also supports other MIC/PICs.

     

    You can find the below link to see the supported PIC :

     

    PICs Supported by MX240, MX480, and MX960 Routers

     

    3) In the context of MX, When we use " INLINE SERVICE"  such as IP FLOW, NAT, GRE, BFD what exactly do we mean by " INLINE"? Are we saying these services are run from PFE not RE?

     

    Yes correct. Historically, routers have required a separate Services Module to provide additional features. One of the key differentiators of the Trio chipset is its ability to integrate network services without the requirement of an additional Services Module. 

     

     



  • 3.  RE: Data plane and Trio Chipset on MX5

    Posted 10-28-2017 06:44

    @adwivedi wrote:

    Hi,

     

    Please find the inline answers :

     

    1)On MX5, when we speak of " Trio Chip Set Architecture" are we only talking about Data plane i.e whole data plane is based on this architecture or does it also include Control plane ?

     

    It also includes control plane. 

     


    Well, from the little of my knowledge, I doubt this. I think trio is only Data Plane Architecture.

     

    From the book, it says

     "the first generation of the trio was born with four specific ASICs: IX (Interface Management for oversubscribed MIC), MQ (Buffering/Queueing block), LU (Lookup Block) and QX (Dence queueing block). The First generation of Trio is found on MPC1, 2, and the
     16x10GE MPCs
     
    Screen Shot 2017-10-28 at 6.58.59 PM.png

    Screen Shot 2017-10-28 at 7.03.19 PM.png