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The most complex of the tasks in a routing chip (that forwards the packets based on layer-3 IP addresses) is the route lookup that involves the longest prefix match on the destination IP address of the packet
The FIB is stored in on-chip or off-chip memories (SRAM, HBM/DRAM, or TCAM)...Take an example of a high-end networking chip with 14.4T bandwidth...These nodes reside in either on-chip or off-chip memories
Answer The Layer 3 interface policer limit for I-chip-based DPCs is 39,000 possible, with 16,000 tested
Question Is indirect next hop supported for VPLS in MX Series routers with I-chip-based DPCs? Answer Prior to Junos OS Release 10.3, indirect next hop is only supported for Layer 3 VPNs
Question What are the QoS differences between the 16-port 10-Gigabit Ethernet MPC and the I-chip-based DPC? Answer Dynamic memory is not supported on the 16-port 10-Gigabit Ethernet MPC
Question Is DiffServ code point (DSCP) classification of MPLS-tagged packets supported on the I-chip-based DPCs? Answer The DSCP classifier is supported on I-chip DPCs as shown in the following table
The following sections cover the technical aspects of the device. First Chiplet-based Networking ASIC Express 5 ASICs are comprised of only two new dies, or chiplets: a high-capacity forwarding chip and a cell-based fabric interface / cell-switching chip
See matching posts in thread - Corrupt flash or DDR3 memory chip...
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With chained or composite next hop, memory usage is optimized in both the kernel and the Packet Forwarding Engine. However, on the I-chip this is available only for the Packet Forwarding Engine. The scaling numbers for I-chip based platforms are: Junos OS Releases prior to 9.5 -- 250,000 to 300,000 labels per prefix Junos OS Release 9.5 and later -- 600,000 labels per prefix Data structure optimization within the Packet Forwarding Engine leads to significant savings in DRAM, with the most gains in the next-hop space and in the Layer 2 descriptors